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74LCX138
LOW VOLTAGE CMOS 3 TO 8 LINE DECODER (INV.) WITH 5V TOLERANT INPUTS
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5V TOLERANT INPUTS HIGH SPEED: tPD = 6.0 ns (MAX.) at VCC = 3V POWER-DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) PCI BUS LEVELS GUARANTEED AT 24mA BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2.0V to 3.6V (1.5V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 138 LATCH-UP PERFORMANCE EXCEEDS 500mA ESD PERFORMANCE: HBM >2000V; MM > 200V
M1 (Micro Package)
T (TSSOP Package)
ORDER CODES : 74LCX138M 74LCX138T If the device is enabled, 3 binary select inputs (A, B and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A or G2B is held high, the decoding function is inhibited and all the 8 outputs go to high. Three enable inputs are provided to ease cascade connection and application of address decoders for memory systems. It has same speed performance at 3.3V than 5V, AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
DESCRIPTION The 74LCX138 is an high-speed CMOS 3 TO 8 LINE DECODER (INVERTING) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for inputs.
PIN CONNECTION AND IEC LOGIC SYMBOLS
May 1999
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INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No 1, 2, 3 4, 5 6 15, 14, 13, 12, 11, 10, 9, 7 8 16 SYMBO L A, B, C G2A, G2B G1 Y0 to Y7 GND VCC NAME AND F UNCTIO N Address Inputs Enable Inputs Enable Input Outputs Ground (0V) Positive Supply Voltage
TRUTH TABLE
INPUT S ENABL E G2B G2A G1 C X X L X X H X X H X X X L L H L L L H L L L H L L L H L L L H H L L H H L L H H L L H H
X:Don't Care
OUTPUTS SELECT B X X X L L H H L L H H A X X X L H L H L H L H Y0 H H H L H H H H H H H Y1 H H H H L H H H H H H Y2 H H H H H L H H H H H Y3 H H H H H H L H H H H Y4 H H H H H H H L H H H Y5 H H H H H H H H L H H Y6 H H H H H H H H H L H Y7 H H H H H H H H H H L
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LOGIC DIAGRAM
Thislogic diagram has notbe used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO VO IIK IOK IO ICC IGND Tstg TL Supply Voltage DC Input Voltage DC Output Voltage (VCC=0V) DC Output Voltage (High or Low State) (note1) DC Input Diode Current DC Output Diode Current (note2) DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Supply Pin Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to + 7.0 -0.5 to + 7.0 -0.5 to + 7.0 -0.5 to VCC + 0.5 - 50 50 50 100 100 -65 to +150 300 Unit V V V V mA mA mA mA mA
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C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. 1) IO absolute maximum rating must be observed 2) VO < GND, VO > VCC
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO VO IOH, IOL IOH, IOL Top dt/dv Input Voltage Output Voltage (V CC=0V) Output Voltage (High or Low State) High or Low Level Output Current (VCC = 3.0 to 3.6V) High or Low Level Output Current (VCC = 2.7 to 3.0V) Operating Temperature: Input Transition Rise or Fall Rate (V CC = 3.0V) (note 2) Parameter Supply Voltage (note 1) Value 2.0 to 3.6 0 to 5.5 0 to 5.5 0 to VCC 24 12 -40 to +85 0 to 10 Unit V V V V mA mA
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C
ns/V
1) Truth Table guaranteed: 1.5V to3.6V 2) VIN from0.8V to 2.0V
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DC SPECIFICATIONS
Symb ol Parameter V CC (V) VIH VIL VOH High Level Input Voltage Low Level Input Voltage High Level Output Voltage 2.7 to 3.6 2.7 to 3.6 2.7 3.0 VOL Low Level Output Voltage 2.7 to 3.6 2.7 3.0 3.0 II Ioff ICC Input Leakage Current Power Off Leakage Current Quiescent Supply Current 2.7 to 3.6 0 2.7 to 3.6 VI = VI H or V IL Test Co nditi ons Value -40 to 85 o C Min. 2.0 0.8 IO=-100 A V CC -0.2 IO=-12 mA IO=-18 mA IO=-24 mA VI = VI H or V IL IO=100 A IO=12 mA IO=16 mA IO=24 mA VI = 0 to 5.5 V VI or VO = 5.5V VI = VCC or GND VI or VO = 3.6 to 5.5V ICC ICC incr. per input 2.7 to 3.6 VIH = VCC -0.6V 2.2 2.4 2.2 0.2 0.4 0.4 0.55 5 100 10 10 500 A A A A V V Max. V V Un it
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol Parameter V CC (V) VOLP VOLV Dynamic Low Voltage Quiet Output (note 1) 3.3 C L = 50 pF V IL = 0 V V IH = 3.3V Test Con dition s Min . Value T A = 25 o C T yp. 0.8 -0.8 V Max. Un it
1) Number ofoutputs defined as "n". Measured with"n-1" outputs switching from HIGH to LOW or LOW t o HIGH. The remaining output is measured in the LOW state.
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = tf = 2.5 ns)
Symb ol Parameter V CC (V) tPLH tPHL tPLH tPHL tPLH tPHL tOSLH tOSHL Propagation Delay Time A, B, C to Y Propagation Delay Time G1 to Y Propagation Delay Time G2 to Y Output to Output Skew Time (note 1, 2) Test Con dition Waveform Value -40 to 85 o C Min. Max. 7.0 1.5 6.0 1.5 1.5 7.5 6.5 7.0 6.0 1.0 Un it
2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 3.0 to 3.6
1 1 1
ns ns ns ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tpHLn|) 2) Parameter guaranteed by design
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74LCX138
CAPACITIVE CHARACTERISTICS
Symb ol Parameter V CC (V) C IN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) 3.3 3.3 3.3 VIN = 0 to VCC VIN = 0 to VCC fIN = 10MHz VIN = 0 or VCC Test Co nditi ons Min. Valu e T A = 25 oC T yp. 6 12 42 Max. pF pF pF Un it
1) CPD isdefined as the value of the IC'sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. Average operting current can be obtained by the following equation. I CC(opr) = CPD * VCC * fIN + ICC
TEST CIRCUIT
CL = 50 pF or equivalent (includes jigand probe capacitance) RL = 500 or equivalent RT = ZOUT of pulse generator (typically 50)
WAVEFORM 1: PROPAGATION DELAYS FOR INVERTING OUTPUTS (f=1MHz; 50% duty cycle)
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WAVEFORM 2: PROPAGATION DELAYS FOR NON-INVERTING OUTPUTS (f=1MHz; 50% duty cycle)
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SO-16 MECHANICAL DATA
DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm TYP. MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
P013H
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TSSOP16 MECHANICAL DATA
mm MIN. A A1 A2 b c D E E1 e K L 0o 0.50 0.05 0.85 0.19 0.09 4.9 6.25 4.3 5 6.4 4.4 0.65 BSC 4o 0.60 8o 0.70 0o 0.020 0.10 0.9 TYP. MAX. 1.1 0.15 0.95 0.30 0.20 5.1 6.5 4.48 0.002 0.335 0.0075 0.0035 0.193 0.246 0.169 0.197 0.252 0.173 0.0256 BSC 4o 0.024 8o 0.028 0.004 0.354 MIN. inch TYP. MAX. 0.433 0.006 0.374 0.0118 0.0079 0.201 0.256 0.176
DIM.
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com .
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